Advances in the technology of integrated circuit (“IC”) production, including increases in lithography resolution to below 100 nm, has resulted in the availability of very high complexity, compact ICs, referred to herein generically as “very large scale integration” or “VLSI” ICs, that provide complex and sophisticated performance, often with enhanced speed and reduced power consumption. Furthermore, due to mass production, many VLSI ICs have become very economical, such that they can provide attractive solutions for a wide range of applications.
Many VLSI ICs are produced at very high resolutions and with very thin transistor gate oxide, so that they operate at low voltages, typically below 1.5V, with reduced power consumption and increased speed. For example, CMOS devices are currently available with resolutions of 14 nm or even 7 nm or less that operate at 0.8V or lower internal voltage.
So as to reduce size and power consumption, many of these VLSI ICs tend to be somewhat specialized in their designs, and include only the features that are required to address their intended applications. For example, many VLSI ICs include input/output (I/O) interfaces that are compatible with only one, or only a few, communication standards. As ICs have become denser and more specialized, different communication protocols have been adopted having signaling and control protocols that are optimized for different applications. Generally, a VLSI IC will be configured only for compatibility with the communication standard(s) that are most commonly in use in the applications that the VLSI IC is most likely to be implemented.
Because modern VLSI ICs provide many advantages in terms of high speed, high density, low power consumption, etc., and because the cost of VLSI ICs is greatly reduced when they can be produced in large quantities, it can be desirable to implement a given VLSI IC design for as many different applications as possible, which can include incorporating existing VLSI IC designs into applications that may not have been foreseen by the designers of the VLSI IC, such as when upgrading legacy apparatus and designs, or designing systems for exotic applications such as deployment in space.
Unfortunately, the limited I/O compatibility and other specialized features of many VLSI ICs can render them difficult or impossible to implement in niche applications such as upgrading legacy technology, or in any circumstances where a communication protocol or other enhanced feature is required that is not supported by the VLSI IC.
In particular, difficulties can arise when interoperability is desired between a low voltage VLSI IC and legacy technologies that communicate using higher voltage protocols, such as PCI (3.3V), SpaceWire (LVDS), I2C (typically 3.3V or 5V open drain), SPI (typically 1.8V or 3.3V), general purpose I/O (typically 5V CMOS or 3.3V LVCMOS), and legacy memory (FLASH, PROM, SRAM, and SDRAM) interfaces (typically 2.5V or 3.3V) or specialized I/O interfaces such as PECL and GTL. For instance, a 1.2V LVCMOS low voltage IC may require conversion to 3.3V LVCMOS or to LVDS.
Due to the thinner gate oxides of most sub-100 nm devices, the individual transistors included in many VLSI ICs simply cannot tolerate the higher voltages at which many legacy communication protocols such as PCI and SPI operate. Furthermore, modern VLSI devices often lack the full complement of output logic and the output current support, or “fan-out,” that is required by these legacy communication standards.
One approach is to include within the same CMOS or other VLSI IC both thin gate oxide transistors, optimized for internal circuits, and thicker gate oxide transistors, optimized for supporting input/output (I/O) circuits at higher voltages. However, this approach increases the integrated circuit manufacturing complexity and cost, typically limiting the thick oxide devices to twice the gate oxide thickness of the internal transistors. As a result, such “dual oxide” I/O transistors typically support interface voltages of only approximately twice the internal transistors, limiting I/O circuits to less than 2 Volts for ICs with less than 1 Volt internal power supply.
Another approach that can provide limited support for legacy communication standards is to configure I/O circuits within the VLSI IC that can tolerate higher voltages by stacking a plurality of transistors and providing a plurality of bias voltages from the power bus, so that no single transistor in the stack is subject to the full output voltage. A typical prior art example is illustrated in FIG. 1. By generating such “protection” voltages, as illustrated, this approach can allow a stacked-transistor I/O circuit to reliably operate at a voltage that is higher than what a single transistor can tolerate.
However, the approach illustrated in FIG. 1 is also typically limited to interfaces that operate at voltages less than twice the breakdown voltage of the I/O transistors, due to the increased complexity of stacking transistors. Also, I/O circuits such as that of FIG. 1, when operating near the breakdown limit of the transistor stack, cannot be used to provide “off-card” signals, i.e. signals that are transmitted beyond the immediate printed circuit board, because the thin gate oxides of the IC transistors are unable to support the large over-shoot and under-shoot voltages that would result on the input/output pins of the IC, due to the longer conduction lengths, as well as transmission line discontinuities caused by the corresponding connector interfaces.
Interoperability challenges when implementing VLSI ICs can also arise when there are differences in output current requirements (“fan-out”), and/or differences in signaling and control requirements. For example, a VLSI IC that offers reduced size and power consumption may support only minimal I/O output current and/or complexity, such that it is suitable for some applications, but not with other applications that require interoperability with a communication protocol that requires higher output current and/or more complex signaling and control. For example, a short-run Serializer/Deserializer (“SerDes”) interface at the low voltage IC level may require conversion to a long-run SerDes.
Another enhanced feature that is required by some niche applications is redundant “cold spare operation,” which is critical for high reliability applications such as space applications, and which the approach of FIG. 1 cannot support. In cold spare operation, unpowered, standby, redundant ICs interface with active devices that may drive their I/O, even when the standby ICs are not powered. The cold spare ICs must survive in this condition, perhaps for many years, before possibly being powered-up to replace a failed device. Additional information regarding cold spare operation can be found for example in U.S. Pat. No. 7,239,177, and in U.S. Pat. No. 5,117,129, both of which are incorporated herein by reference for all purposes.
The approach of FIG. 1 cannot support cold spare operation because, when the higher voltage I/O circuits of the standby ICs are not powered, the bias circuits are inoperative and are thus unable to generate the bias (i.e. “protection”) voltages required for reliable operation. In the absence of these “protection” voltages, the approach of FIG. 1 would be limited to the voltage that a single transistor can reliably tolerate in “cold spare” operation. More importantly, if an elevated voltage were applied to an I/O circuit using the approach of FIG. 1 while in “cold spare” operation, catastrophic device failure would quickly occur, due to the voltage overstress condition created on the thin-gate oxides of the I/O circuit transistors.
Even when designing new VLSI ICs, it can be difficult to include sufficient I/O compatibility and other features in the IC to enable its use in a wide variety of applications, without unduly increasing the size, complexity, and power consumption of the IC.
One approach to providing high density ICs that are more flexible and less specialized is the multi-function “System on a Chip” or “SoC” approach. These complex SoC designs enable a single IC to support many use applications and therefore greatly reduce the need to develop derivative ICs, by providing a large number of functions on a single IC and allowing each application to select which of the available functions will be used.
Another approach to providing high density ICs that are more flexible and less specialized is the multi-function “Field Programmable Gate Array” or “FPGA” approach. FPGAs are personalized by programming configurable circuits according to individual application requirements.
Of course, a significant disadvantage of these approaches is that the power that is supplied to unused portions of the FPGA or SoC is wasted. In applications where large portions of the FPGA or SoC design are utilized, the adverse impacts of power consumed by unused portions of the FPGA or SoC are somewhat minimized. However, in other applications where only small portions of the FPGA or SoC design are utilized, the adverse impact of power consumed by unused portions of the FPGA or SoC is maximized.
One approach is to incorporate power management features into the system to optimize the power consumption of each use application. For example, on-die power gating is often included in portable electronics to enable dynamic power control of functions within the SoC by supplying power only to those circuits of the SoC that are required for a given application. However, while on-die power gating is an effective method for reducing power consumption within a SoC, it can be challenging to implement in advanced technology nodes due to long-term reliability challenges, for example related to thermal management (hot spots) and wire wear out (electromigration). These long-term reliability challenges are even more problematic in space applications, due to prolonged mission durations, elevated operating temperatures and limited thermal management options.
An approach that can address almost any type of communication incompatibility and/or lack of other desired VLSI features is to provide intervening circuitry, referred to herein generically as an interface IC, or sometimes generically as a “buffer” or “transceiver,” to provide voltage and/or logic interoperability between the VLSI IC and one or more legacy or otherwise incompatible communication interfaces, and/or to otherwise provide required feature enhancements. In the case of a low pin count communication standard, a discrete component interface can sometimes be implemented on the same printed circuit board on which the VLSI IC is installed. However, certain “extra” I/O control signals may be required for direction control, tristate control, clocking or similar functions of such “buffer” devices. Such extra control signals may not be available from the VLSI IC or, if available, may represent extra I/O and cost at the VLSI IC package level.
For higher pin count interfaces, it is often necessary to implement the transceiver, buffer, or other interface on a field-programmable gate array (FPGA) or application specific integrated circuit (ASIC) separately mounted on the printed circuit board with the VLSI IC. Such interfaces typically consume significant additional power and space, and in the case of an FPGA or ASIC there is also typically a high additional cost. Furthermore, this approach can impose a significant speed penalty, due to speed-of-light delays and added capacitance that arise from the interconnections between the transceiver or other interface and the VLSI IC.
What is needed therefore is a device and method of configuration thereof that can flexibly provide at least one enhanced feature that is lacking from a VLSI IC, such as interoperability between the VLSI IC and interface standards that are incompatible with the VLSI IC, for example because they require higher voltages, higher currents, and/or signaling and/or control configurations that are not supported by the VLSI IC, and/or where cold spare support, power gating, and/or another enhanced feature is required but is not supported by the VLSI IC, without requiring an interface buffer or transceiver that is external to the device.